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A Design Tool for the Specification and the Simulation of Array Processors Architectures -- Application to Image Processing: The Extraction of Regions of Interests
Strasbourg, France July 24-July 26
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASAP.1995.5229361995 IEEE International Conference on ...
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G. Ramstein, O. Deforges, P. Bakowski, "A Design Tool for the Specification and the Simulation of Array Processors Architectures -- Application to Image Processing: The Extraction of Regions of Interests," Application-Specific Systems, Architectures and Processors, IEEE International Conference on, pp. 322, 1995 IEEE International Conference on Application-Specific Array Processors (ASAP'95), 1995.
 
 
BibTex
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@article{ 10.1109/ASAP.1995.522936,
author = {G. Ramstein and O. Deforges and P. Bakowski},
title = {A Design Tool for the Specification and the Simulation of Array Processors Architectures -- Application to Image Processing: The Extraction of Regions of Interests},
journal ={Application-Specific Systems, Architectures and Processors, IEEE International Conference on},
volume = {0},
year = {1995},
issn = {1063-6862},
pages = {322},
doi = {http://doi.ieeecomputersociety.org/10.1109/ASAP.1995.522936},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Application-Specific Systems, Architectures and Processors, IEEE International Conference on
TI - A Design Tool for the Specification and the Simulation of Array Processors Architectures -- Application to Image Processing: The Extraction of Regions of Interests
SN - 1063-6862
SP
EP
A1 - G. Ramstein,
A1 - O. Deforges,
A1 - P. Bakowski,
PY - 1995
VL - 0
JA - Application-Specific Systems, Architectures and Processors, IEEE International Conference on
ER -
 
G. Ramstein, SEI, IRESTE, Cedex, France
O. Deforges, SEI, IRESTE, Cedex, France
P. Bakowski, SEI, IRESTE, Cedex, France
This paper deals with a CAD tool dedicated to the design and the simulation of specific Array Processor architectures. These architectures are described into a specific notation which includes major characteristics of the VHDL syntax. This language provides a very concise and legible means to specify Array Processors. A preprocessor generates full standard VHDL code describing the behavior of the designed architecture. An original application to image processing is given: the design of a specific architecture for the extraction of regions of interests.
Citation:
G. Ramstein, O. Deforges, P. Bakowski, "A Design Tool for the Specification and the Simulation of Array Processors Architectures -- Application to Image Processing: The Extraction of Regions of Interests," asap, pp.322, 1995 IEEE International Conference on Application-Specific Array Processors (ASAP'95), 1995
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