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An Architectural Design For Parallel Fractal Compression
Chicago, IL August 19-August 23
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASAP.1996.5427961996 IEEE International Conference on ...
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K.P. Acken, H.N. Kim, M.J. Irwin, R.M. Owens, "An Architectural Design For Parallel Fractal Compression," Application-Specific Systems, Architectures and Processors, IEEE International Conference on, pp. 3, 1996 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'96), 1996.
 
 
BibTex
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@article{ 10.1109/ASAP.1996.542796,
author = {K.P. Acken and H.N. Kim and M.J. Irwin and R.M. Owens},
title = {An Architectural Design For Parallel Fractal Compression},
journal ={Application-Specific Systems, Architectures and Processors, IEEE International Conference on},
volume = {0},
year = {1996},
issn = {1063-6862},
pages = {3},
doi = {http://doi.ieeecomputersociety.org/10.1109/ASAP.1996.542796},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Application-Specific Systems, Architectures and Processors, IEEE International Conference on
TI - An Architectural Design For Parallel Fractal Compression
SN - 1063-6862
SP
EP
A1 - K.P. Acken,
A1 - H.N. Kim,
A1 - M.J. Irwin,
A1 - R.M. Owens,
PY - 1996
KW - data compression; image coding; encoding; image processing; parallel architectures; application specific integrated circuits; fractals; architectural design; parallel fractal compression; archival storage; encoding algorithm; quad-tree fractal encoding algorithm; ASIC parallel image processing; gray-scale images; speed improvements; circuit levels
VL - 0
JA - Application-Specific Systems, Architectures and Processors, IEEE International Conference on
ER -
 
K.P. Acken, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
H.N. Kim, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
M.J. Irwin, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
R.M. Owens, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
Fractal image compression has many features that makes it a powerful compression scheme, but it has been mainly restricted to archival storage due to its time consuming encoding algorithm. In this paper, we take a known quad-tree fractal encoding algorithm and design an ASIC parallel image processing array that can encode reasonably sized gray-scale images in real-time. In designing this architecture, we include novel optimizations that result in speed improvements at the algorithmic, architectural, and circuit levels.
Index Terms:
data compression; image coding; encoding; image processing; parallel architectures; application specific integrated circuits; fractals; architectural design; parallel fractal compression; archival storage; encoding algorithm; quad-tree fractal encoding algorithm; ASIC parallel image processing; gray-scale images; speed improvements; circuit levels
Citation:
K.P. Acken, H.N. Kim, M.J. Irwin, R.M. Owens, "An Architectural Design For Parallel Fractal Compression," asap, pp.3, 1996 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'96), 1996
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