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A Coalescing-Partitioning Algorithm for Optimizing Processor Specification and Task Allocation
Chicago, IL August 19-August 23
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASAP.1996.5428281996 IEEE International Conference on ...
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This paper considers the design problems of processor specification and task allocation for embedded computer systems. A graph partitioning-based representation is proposed that allows these problems to be solved concurrently. A custom design automation algorithm based on this representation is then presented. This algorithm, named CP*-2, was benchmarked against two baseline algorithms on a combination of real and synthetic test cases with respect to two figures of merit: hardware cost and run-time. The real test cases are based on commercially developed automotive applications and the benchmark algorithms consist of heuristic and simulated annealing approaches. On average, CP*-2 was found to generate solutions with quality comparable to simulated annealing with up to an order of magnitude improvement in run-time.
Citation:
Jim Beck, Dan Siewiorek, "A Coalescing-Partitioning Algorithm for Optimizing Processor Specification and Task Allocation," asap, pp.342, 1996 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'96), 1996
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