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A flexible data-interlacing architecture for full-search block-matching algorithm
Zurich, SWITZERLAND July 14-July 16
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASAP.1997.6068161997 IEEE International Conference on ...
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Yeong-Kang Lai, Liang-Gee Chen, Yung-Pin Lee, "A flexible data-interlacing architecture for full-search block-matching algorithm," Application-Specific Systems, Architectures and Processors, IEEE International Conference on, pp. 96, 1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'97), 1997.
 
 
BibTex
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@article{ 10.1109/ASAP.1997.606816,
author = {Yeong-Kang Lai and Liang-Gee Chen and Yung-Pin Lee},
title = {A flexible data-interlacing architecture for full-search block-matching algorithm},
journal ={Application-Specific Systems, Architectures and Processors, IEEE International Conference on},
volume = {0},
year = {1997},
issn = {1063-6862},
pages = {96},
doi = {http://doi.ieeecomputersociety.org/10.1109/ASAP.1997.606816},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Application-Specific Systems, Architectures and Processors, IEEE International Conference on
TI - A flexible data-interlacing architecture for full-search block-matching algorithm
SN - 1063-6862
SP
EP
A1 - Yeong-Kang Lai,
A1 - Liang-Gee Chen,
A1 - Yung-Pin Lee,
PY - 1997
KW - motion estimation; flexible data-interlacing architecture; data-reuse; cascading strategies; search ranges; pixel rates; external memory accesses; full search block-matching algorithm
VL - 0
JA - Application-Specific Systems, Architectures and Processors, IEEE International Conference on
ER -
 
Yeong-Kang Lai, Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Liang-Gee Chen, Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Yung-Pin Lee, Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
This paper describes a data-interlacing architecture with two-dimensional (2-D) data-reuse for full-search block-matching algorithm. Based on some cascading strategies, the same chips can be flexibly cascaded for different block sizes, search ranges, and pixel rates. In addition, the cascading chips can efficiently reuse data to decrease external memory accesses and achieve a high throughput rate. Our results demonstrate that the architecture with 2-D data-reuse is a flexible, low-pin-counts, high-throughput, and cascadable solution for full search block-matching algorithm.
Index Terms:
motion estimation; flexible data-interlacing architecture; data-reuse; cascading strategies; search ranges; pixel rates; external memory accesses; full search block-matching algorithm
Citation:
Yeong-Kang Lai, Liang-Gee Chen, Yung-Pin Lee, "A flexible data-interlacing architecture for full-search block-matching algorithm," asap, pp.96, 1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'97), 1997
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