On core and more: a design perspective for systems-on-a-chip

Zurich, SWITZERLAND July 14-July 16

DOI Bookmark:

http://doi.ieeecomputersociety.org/10.1109/ASAP.1997.606850

1997 IEEE International Conference on ...

	This Article
	PURCHASE ARTICLE: $19 PDF HTML IEEE Xplore Subscribers
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by S. Pees Articles by M. Vaupel Articles by V. Zivojnovic Articles by H. Meyr

	ASCII Text	x
	S. Pees, M. Vaupel, V. Zivojnovic, H. Meyr, "On core and more: a design perspective for systems-on-a-chip," Application-Specific Systems, Architectures and Processors, IEEE International Conference on, pp. 448, 1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'97), 1997.

	BibTex	x
	@article{ 10.1109/ASAP.1997.606850, author = {S. Pees and M. Vaupel and V. Zivojnovic and H. Meyr}, title = {On core and more: a design perspective for systems-on-a-chip}, journal ={Application-Specific Systems, Architectures and Processors, IEEE International Conference on}, volume = {0}, year = {1997}, issn = {1063-6862}, pages = {448}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASAP.1997.606850}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Application-Specific Systems, Architectures and Processors, IEEE International Conference on TI - On core and more: a design perspective for systems-on-a-chip SN - 1063-6862 SP EP A1 - S. Pees, A1 - M. Vaupel, A1 - V. Zivojnovic, A1 - H. Meyr, PY - 1997 KW - computational complexity; design perspective; systems-on-a-chip; highly competitive telecommunications market; design environment; system design; fast simulation; intellectual property; HW/SW co-design; system level performance evaluation VL - 0 JA - Application-Specific Systems, Architectures and Processors, IEEE International Conference on ER -

S. Pees, Integrated Syst. for Signal Process., Aachen Univ. of Technol., Germany

M. Vaupel, Integrated Syst. for Signal Process., Aachen Univ. of Technol., Germany

V. Zivojnovic, Integrated Syst. for Signal Process., Aachen Univ. of Technol., Germany

H. Meyr, Integrated Syst. for Signal Process., Aachen Univ. of Technol., Germany

In this survey, key drivers in design methodology are provided that enable successful design of systems-on-a-chip for the highly competitive telecommunications market. Main components of a design environment are described that fulfill the requirements of today's system design: efficient verification by means of fast simulation, integration of intellectual property, support of HW/SW co-design by means of a generic machine description language, generation of dedicated hardware blocks for high speed applications, and the link from system level performance evaluation to implementations in hardware and software.

Index Terms:

computational complexity; design perspective; systems-on-a-chip; highly competitive telecommunications market; design environment; system design; fast simulation; intellectual property; HW/SW co-design; system level performance evaluation

Citation:

S. Pees, M. Vaupel, V. Zivojnovic, H. Meyr, "On core and more: a design perspective for systems-on-a-chip," asap, pp.448, 1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'97), 1997

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.