A 550 Mb/s Radix-4 Bit-level Pipelined 16-State 0.25-?m CMOS Viterbi Decoder

Boston, Massachusetts July 10-July 12

DOI Bookmark:

http://doi.ieeecomputersociety.org/10.1109/ASAP.2000.862390

12th IEEE International Conference on ...

	This Article
	PURCHASE ARTICLE: $19 PDF HTML IEEE Xplore Subscribers
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by V.S. Gierenz Articles by O. Weiss Articles by T.G. Noll Articles by I. Carew Articles by J. Ashley Articles by R. Karabed

	ASCII Text	x
	V.S. Gierenz, O. Weiss, T.G. Noll, I. Carew, J. Ashley, R. Karabed, "A 550 Mb/s Radix-4 Bit-level Pipelined 16-State 0.25-?m CMOS Viterbi Decoder," Application-Specific Systems, Architectures and Processors, IEEE International Conference on, pp. 195, 12th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'00), 2000.

	BibTex	x
	@article{ 10.1109/ASAP.2000.862390, author = {V.S. Gierenz and O. Weiss and T.G. Noll and I. Carew and J. Ashley and R. Karabed}, title = {A 550 Mb/s Radix-4 Bit-level Pipelined 16-State 0.25-?m CMOS Viterbi Decoder}, journal ={Application-Specific Systems, Architectures and Processors, IEEE International Conference on}, volume = {0}, year = {2000}, issn = {1063-6862}, pages = {195}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASAP.2000.862390}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Application-Specific Systems, Architectures and Processors, IEEE International Conference on TI - A 550 Mb/s Radix-4 Bit-level Pipelined 16-State 0.25-?m CMOS Viterbi Decoder SN - 1063-6862 SP EP A1 - V.S. Gierenz, A1 - O. Weiss, A1 - T.G. Noll, A1 - I. Carew, A1 - J. Ashley, A1 - R. Karabed, PY - 2000 KW - disk-drive read channels KW - high-speed Viterbi decoder KW - radix-4 add-compare-select KW - redundant number representations KW - bit-level pipelining KW - CMOS technology KW - full-custom macros KW - datapath generator assisted design KW - 0.25 micron KW - 550 MHz VL - 0 JA - Application-Specific Systems, Architectures and Processors, IEEE International Conference on ER -

V.S. Gierenz, Institute of Technology RWTH Aachen

O. Weiss, Institute of Technology RWTH Aachen

T.G. Noll, Institute of Technology RWTH Aachen

I. Carew, Infineon Technologies

J. Ashley, Infineon Technologies

R. Karabed, Infineon Technologies

In today's high-speed disk drive read channel ICs maximum likelihood detection using the Viterbi algorithm is a key component in reconstructing digital data sequences. The presented Viterbi decoder was realized in a 0.25-?m CMOS technology. Using the proposed comparison approach, it achieves a throughput rate of 550 Mb/s.

Index Terms:

disk-drive read channels, high-speed Viterbi decoder, radix-4 add-compare-select, redundant number representations, bit-level pipelining, CMOS technology, full-custom macros, datapath generator assisted design, 0.25 micron, 550 MHz

Citation:

V.S. Gierenz, O. Weiss, T.G. Noll, I. Carew, J. Ashley, R. Karabed, "A 550 Mb/s Radix-4 Bit-level Pipelined 16-State 0.25-?m CMOS Viterbi Decoder," asap, pp.195, 12th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'00), 2000

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.