loading...
A Hardware Algorithm for Variable-Precision Logarithm
Boston, Massachusetts July 10-July 12
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASAP.2000.86239212th IEEE International Conference on ...
 This Article 
 
PDF
HTML
 
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Javier Hormigo, University of Malaga
Julio Villalba, University of Malaga
Michael J. Schulte, Lehigh University
This paper presents an efficient hardware algorithm for variable-precision logarithm. The algorithm uses an iterative technique that employs table lookups and polynomial approximations. Compared to similar algorithms, it reduces the number of fixed-precision operations by avoiding full precision computations and dynamically varying the precision of intermediate results. It also uses significantly smaller tables than related algorithms. Fora specified hardware implementation, the algorithm requires fewer than 2 x L**2 fixed-precision multiplications to evaluate the logarithm to L words of precision. An error analysis for the algorithm is also presented.
Index Terms:
Computer arithmetic, variable-precision, logarithm, error analysis
Citation:
Javier Hormigo, Julio Villalba, Michael J. Schulte, "A Hardware Algorithm for Variable-Precision Logarithm," asap, pp.215, 12th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'00), 2000
Usage of this product signifies your acceptance of the Terms of Use.