Although arrays of SIMD PEs can be built with very high operating frequencies, problems exist in keeping the array busy. The inherent mismatch between host and array makes it difficult to maintain high array utilization: either the rate of instruction issue is very low or PE data locality is compromised, having the same effect. Our solution is based on an array control unit (ACU) design that expands macroinstructions in two stages, first by data tile and then into microinstructions. The expansion itself solves the issue problem; decoupling the expansion modalities maintains data locality. Several issues involving host/ACU interaction needed to be resolved to affect this solution.
Index Terms:
Parallel Architecture, Application Specific Array Processors, Array Control Unit, SIMD processing
Citation:
Martin C. Herbordt, Honghai Zhang, Calvin Lin, Hong Rao, Jade Cravy, "Control for High-Speed PE Arrays," asap, pp.247, 12th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'00), 2000