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256-State Rate 1/2 Viterbi Decoder on TTA Processor
Samos, Greece July 23-July 25
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASAP.2005.52005 IEEE International Conference on ...
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Perttu Salmela, Tuomas Jarvinen, Teemu Sipila, Jarmo Takala, "256-State Rate 1/2 Viterbi Decoder on TTA Processor," Application-Specific Systems, Architectures and Processors, IEEE International Conference on, pp. 370-378, 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05), 2005.
 
 
BibTex
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@article{ 10.1109/ASAP.2005.5,
author = {Perttu Salmela and Tuomas Jarvinen and Teemu Sipila and Jarmo Takala},
title = {256-State Rate 1/2 Viterbi Decoder on TTA Processor},
journal ={Application-Specific Systems, Architectures and Processors, IEEE International Conference on},
volume = {0},
year = {2005},
issn = {1063-6862},
pages = {370-378},
doi = {http://doi.ieeecomputersociety.org/10.1109/ASAP.2005.5},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Application-Specific Systems, Architectures and Processors, IEEE International Conference on
TI - 256-State Rate 1/2 Viterbi Decoder on TTA Processor
SN - 1063-6862
SP370
EP378
A1 - Perttu Salmela,
A1 - Tuomas Jarvinen,
A1 - Teemu Sipila,
A1 - Jarmo Takala,
PY - 2005
KW - null
VL - 0
JA - Application-Specific Systems, Architectures and Processors, IEEE International Conference on
ER -
 
Perttu Salmela, Institute of Digital and Computer Systems Tampere University of Technology,Tampere, Finland
Tuomas Jarvinen, Institute of Digital and Computer Systems Tampere University of Technology,Tampere, Finland
Teemu Sipila, Institute of Digital and Computer Systems Tampere University of Technology,Tampere, Finland
Jarmo Takala, Nokia Mobile Phones, Oulu, Finland

Efficient and flexible Viterbi decoding is an important problem in implementation of modern telecommunications systems. In this paper, a 256-state, rate 1/2 Viterbi decoder is implemented on a transport triggered architecture processor. Due to the processor-based platform, the implementation is flexible and it can achieve relatively high decoding speed. The decoder is implemented by tailoring the processor to meet the requirements of Viterbi decoding. The processor is enhanced with a number of special function units, which accelerate the decoding. As a result, the decoding can be carried out efficiently on a processor-based platform.

Citation:
Perttu Salmela, Tuomas Jarvinen, Teemu Sipila, Jarmo Takala, "256-State Rate 1/2 Viterbi Decoder on TTA Processor," asap, pp.370-378, 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05), 2005
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