For the first time, we implemented a reconfigurable load-balanced TDM switch IC with SERDES interface circuits for high speed networking applications. An N times N TDM switch could be constructed recursively from the TDM switch IC to achieve switching capacity of hundred gigabits per second or higher. The TDM switch IC contained a digital 8 times 8 TDM switch core with 8B10B CODECs and analog SERDES I/O interfaces. In the I/O interfaces, eight 2.56/3.2Gbps dual-mode 16/20:1 SERDES with CML buffers were developed. The 16/20:1 instead of 8/10:1 serializer and deserializer were used to reduce the required operating frequency in the switch core by half. New half-rate architectures and all static CMOS gates were used in the 16/20:1 serializer and deserializer for the low power consumption. A wide-band CML I/O buffer with our patented PMOS active load scheme was developed. All implementation were based on the 0.18 mum CMOS technology. Our implementation showed a 20 Gbps switching capacity for the 8 times 8 TDM switch IC.
Index Terms:
0.18 micron, Birkhoff-von Neumann symmetric TDM switch IC, SERDES interfaces, load-balanced TDM switch IC, high speed networking, digital TDM switch, 8B10B CODEC, analog SERDES I/O interfaces, dual-mode SERDES, half-rate architectures, all static CMOS gates, low power consumption, wide-band CML buffer, PMOS active load scheme, CMOS technology, 20 Gbit/s
Citation:
null Yu-Hao Hsu, null Min-Sheng Kao, null Hou-Cheng Tzeng, null Ching-Te Chiu, null Jen-Ming Wu, null Shuo-Hung Hsu, "A 20 Gbps Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC with SERDES Interfaces," asp-dac, pp.102-103, 2007 Asia and South Pacific Design Automation Conference, 2007
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