A 90nm 8?16 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations

Yokohama January 23-January 26

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http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2007.357971

2007 Asia and South Pacific Design Au ...

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	ASCII Text	x
	Y. Sugihara, M. Kotani, K. Katsuki, K. Kobayashi, H. Onodera, "A 90nm 8?16 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations," Asia and South Pacific Design Automation Conference, pp. 122-123, 2007 Asia and South Pacific Design Automation Conference, 2007.

	BibTex	x
	@article{ 10.1109/ASPDAC.2007.357971, author = {Y. Sugihara and M. Kotani and K. Katsuki and K. Kobayashi and H. Onodera}, title = {A 90nm 8?16 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations}, journal ={Asia and South Pacific Design Automation Conference}, volume = {0}, year = {2007}, isbn = {1-4244-0629-3}, pages = {122-123}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2007.357971}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asia and South Pacific Design Automation Conference TI - A 90nm 8?16 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations SN - 1-4244-0629-3 SP122 EP123 A1 - Y. Sugihara, A1 - M. Kotani, A1 - K. Katsuki, A1 - K. Kobayashi, A1 - H. Onodera, PY - 2007 KW - 90 nm KW - within-die variations KW - LUT-based FPGA device KW - ring oscillators KW - placement optimization KW - simple model circuit VL - 0 JA - Asia and South Pacific Design Automation Conference ER -

Y. Sugihara, Dept. of Commun.&Comput. Engeineering, Kyoto Univ.

M. Kotani, Dept. of Commun.&Comput. Engeineering, Kyoto Univ.

K. Katsuki, Dept. of Commun.&Comput. Engeineering, Kyoto Univ.

K. Kobayashi, Dept. of Commun.&Comput. Engeineering, Kyoto Univ.

H. Onodera, Dept. of Commun.&Comput. Engeineering, Kyoto Univ.

We have fabricated an LUT-based FPGA device with functionalities measuring within-die variations in a 90nm process. Measured variations are used to configure each device to maximize the operating frequency by allocating critical paths in faster portions. Variations are measured using ring oscillators implemented as a configuration of the FPGA. Placement optimization using a simple model circuit reveals that performance of the circuit is enhanced by 4% in average, which is the same amount as the measured within-die variations. The yield is enhanced by 32% to the worst case.

Index Terms:

90 nm, within-die variations, LUT-based FPGA device, ring oscillators, placement optimization, simple model circuit

Citation:

Y. Sugihara, M. Kotani, K. Katsuki, K. Kobayashi, H. Onodera, "A 90nm 8?16 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations," asp-dac, pp.122-123, 2007 Asia and South Pacific Design Automation Conference, 2007

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