Power and Memory Bandwidth Reduction of an H.264/AVC HDTV Decoder LSI with Elastic Pipeline Architecture

Yokohama January 23-January 26

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http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2007.358001

2007 Asia and South Pacific Design Au ...

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	ASCII Text	x
	Kentaro Kawakami, Mitsuhiko Kuroda, Hiroshi Kawaguchi, Masahiko Yoshimoto, "Power and Memory Bandwidth Reduction of an H.264/AVC HDTV Decoder LSI with Elastic Pipeline Architecture," Asia and South Pacific Design Automation Conference, pp. 292-297, 2007 Asia and South Pacific Design Automation Conference, 2007.

	BibTex	x
	@article{ 10.1109/ASPDAC.2007.358001, author = {Kentaro Kawakami and Mitsuhiko Kuroda and Hiroshi Kawaguchi and Masahiko Yoshimoto}, title = {Power and Memory Bandwidth Reduction of an H.264/AVC HDTV Decoder LSI with Elastic Pipeline Architecture}, journal ={Asia and South Pacific Design Automation Conference}, volume = {0}, year = {2007}, isbn = {1-4244-0629-3}, pages = {292-297}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2007.358001}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asia and South Pacific Design Automation Conference TI - Power and Memory Bandwidth Reduction of an H.264/AVC HDTV Decoder LSI with Elastic Pipeline Architecture SN - 1-4244-0629-3 SP292 EP297 A1 - Kentaro Kawakami, A1 - Mitsuhiko Kuroda, A1 - Hiroshi Kawaguchi, A1 - Masahiko Yoshimoto, PY - 2007 KW - null VL - 0 JA - Asia and South Pacific Design Automation Conference ER -

Kentaro Kawakami, Department of Informatics and Electronics, Graduate School of Science and Technology, Kobe Universit

Mitsuhiko Kuroda, Department of Informatics and Electronics, Graduate School of Science and Technology, Kobe Universit

Hiroshi Kawaguchi, Department of Computer and Systems Engineering, Kobe University, Kobe, Hyogo 657-8501. Tel: +81-78-8

Masahiko Yoshimoto, Department of Computer and Systems Engineering, Kobe University, Kobe, Hyogo 657-8501. Tel: +81-78-8

We propose an elastic pipeline that can apply dynamic voltage scaling (DVS) to hardwired logic circuits. The proposed pipeline can also reduce a required local bus bandwidth. In order to demonstrate its feasibility, a hardwired H.264/AVC HDTV decoder is designed as a real-time application. The proposed architecture reduces a power to 56% in a 90-nm process technology, compared to the conventional clock-gating scheme or a local bus bandwidth to 37.2%.

Citation:

Kentaro Kawakami, Mitsuhiko Kuroda, Hiroshi Kawaguchi, Masahiko Yoshimoto, "Power and Memory Bandwidth Reduction of an H.264/AVC HDTV Decoder LSI with Elastic Pipeline Architecture," asp-dac, pp.292-297, 2007 Asia and South Pacific Design Automation Conference, 2007

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