Implementation of a Real Time Programmable Encoder for Low Density Parity Check Code on a Reconfigurable Instruction Cell Architecture

Yokohama January 23-January 26

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http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2007.358049

2007 Asia and South Pacific Design Au ...

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	Zahid Khan, Tughrul Arslan, "Implementation of a Real Time Programmable Encoder for Low Density Parity Check Code on a Reconfigurable Instruction Cell Architecture," Asia and South Pacific Design Automation Conference, pp. 583-588, 2007 Asia and South Pacific Design Automation Conference, 2007.

	BibTex	x
	@article{ 10.1109/ASPDAC.2007.358049, author = {Zahid Khan and Tughrul Arslan}, title = {Implementation of a Real Time Programmable Encoder for Low Density Parity Check Code on a Reconfigurable Instruction Cell Architecture}, journal ={Asia and South Pacific Design Automation Conference}, volume = {0}, year = {2007}, isbn = {1-4244-0629-3}, pages = {583-588}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2007.358049}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asia and South Pacific Design Automation Conference TI - Implementation of a Real Time Programmable Encoder for Low Density Parity Check Code on a Reconfigurable Instruction Cell Architecture SN - 1-4244-0629-3 SP583 EP588 A1 - Zahid Khan, A1 - Tughrul Arslan, PY - 2007 KW - null VL - 0 JA - Asia and South Pacific Design Automation Conference ER -

Zahid Khan, System Level Integration Group, The University of Edinburgh, Mayfield Road, Edinburgh, EH9 3JL, Scot

Tughrul Arslan, System Level Integration Group, The University of Edinburgh, Mayfield Road, Edinburgh, EH9 3JL, Scot

This paper presents a real time programmable irregular Low Density Parity Check (LDPC) Encoder as specified in the IEEE P802.16E/D7 standard. The encoder is programmable for frame sizes from 576 to 2304 and for five different code rates. H matrix is efficiently generated and stored for a particular frame size and code rate. The encoder is implemented on Reconfigurable Instruction Cell Architecture (RA) which has recently emerged as an ultra low power, high performance, ANSI-C programmable embedded core. Different general and architecture specific optimization techniques are applied to enhance the throughput. With RA, a throughput from 10 to 19 Mbps has been achieved.

Citation:

Zahid Khan, Tughrul Arslan, "Implementation of a Real Time Programmable Encoder for Low Density Parity Check Code on a Reconfigurable Instruction Cell Architecture," asp-dac, pp.583-588, 2007 Asia and South Pacific Design Automation Conference, 2007

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