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A Multiplexor Based Test Method for Self-Timed Circuits
New York City, New York, USA March 14-March 16
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASYNC.2005.511th IEEE International Symposium on ...
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Frank te Beest, Philips Technology Incubator
Ad Peeters, Philips Technology Incubator
A new test method for self-timed circuits is presented that only uses multiplexers to make the majority of combinational feedback loops testable. Combinational feedback loops are problematic for testing, since they introduce sequential behavior in a circuit. Traditionally feedback loops are broken with scan latches or even scan flip-flops, which causes not only a large area overhead, but also have a large impact on performance. The method we present significantly reduces the cost of testing a self-timed circuit, while it retains all the benefits of traditional scan test methods. Most importantly, the method remains fully compatible with standard combinational test pattern generation tools and provides up to 100% stuck-at fault coverage. With the presented test method it becomes cost effective to use scan test for a self-timed circuit without the need to add new specialized cells to a standard cell library.
Citation:
Frank te Beest, Ad Peeters, "A Multiplexor Based Test Method for Self-Timed Circuits," async, pp.166-175, 11th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'05), 2005
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