In this paper, we propose the design of On-chip and Off-chip Interfaces adapted to a Globally Asynchronous Locally Synchronous (GALS) Network-on-Chip (NoC) architecture. The proposed On-chip interface not only handles the resynchronization between the synchronous and asynchronous NoC domains, but also implements NoC communication priorities. This design is based on existing multi-clock synchronization fifos based on Gray code, and is adapted to standard implementation tools. Concerning Off-chip communications, a new concept of mixed synchronous/asynchronous dual mode NoC port is proposed as an efficient Off-chip NoC interface for NoCbased open-platform prototyping. These interfaces have been successfully implemented in a 0.13um CMOS technology.