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Interface Design for Rationally Clocked GALS Systems
Grenoble, France March 13-March 15
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASYNC.2006.1912th IEEE International Symposium on ...
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Joycee Mekie, Supratik Chakraborty, D.K. Sharma, Girish Venkataramani, P. S. Thiagarajan, "Interface Design for Rationally Clocked GALS Systems," Asynchronous Circuits and Systems, International Symposium on, pp. 160-171, 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06), 2006.
 
 
BibTex
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@article{ 10.1109/ASYNC.2006.19,
author = {Joycee Mekie and Supratik Chakraborty and D.K. Sharma and Girish Venkataramani and P. S. Thiagarajan},
title = {Interface Design for Rationally Clocked GALS Systems},
journal ={Asynchronous Circuits and Systems, International Symposium on},
volume = {0},
year = {2006},
issn = {1522-8681},
pages = {160-171},
doi = {http://doi.ieeecomputersociety.org/10.1109/ASYNC.2006.19},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Asynchronous Circuits and Systems, International Symposium on
TI - Interface Design for Rationally Clocked GALS Systems
SN - 1522-8681
SP160
EP171
A1 - Joycee Mekie,
A1 - Supratik Chakraborty,
A1 - D.K. Sharma,
A1 - Girish Venkataramani,
A1 - P. S. Thiagarajan,
PY - 2006
KW - null
VL - 0
JA - Asynchronous Circuits and Systems, International Symposium on
ER -
 
Joycee Mekie, Indian Institute of Technology, Bombay
Supratik Chakraborty, Indian Institute of Technology, Bombay
D.K. Sharma, Indian Institute of Technology, Bombay
Girish Venkataramani, Carnegie Mellon University
P. S. Thiagarajan, National University of Singapore
We investigate the problem of designing interface circuits for rationally clocked modules in GALS systems. As a key contribution, we show that knowledge of flow-control protocols can be used to significantly optimize synchronization mechanisms. We present delayaugmented netcharts as a formalism for representing communication protocols and describe techniques to analyze them. We use the results of our analysis to design a simple yet generic interface that is optimized for the given protocol and is free from synchronization failures. We show by means of case studies the inherent advantages of our methodology over an existing solution technique.
Citation:
Joycee Mekie, Supratik Chakraborty, D.K. Sharma, Girish Venkataramani, P. S. Thiagarajan, "Interface Design for Rationally Clocked GALS Systems," async, pp.160-171, 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06), 2006
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