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Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis
Berkeley, California March 12-March 14
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASYNC.2007.1013th IEEE International Symposium on ...
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Tiberiu Chelcea, Girish Venkataramani, Seth C. Goldstein, "Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis," Asynchronous Circuits and Systems, International Symposium on, pp. 117-128, 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07), 2007.
 
 
BibTex
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@article{ 10.1109/ASYNC.2007.10,
author = {Tiberiu Chelcea and Girish Venkataramani and Seth C. Goldstein},
title = {Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis},
journal ={Asynchronous Circuits and Systems, International Symposium on},
volume = {0},
year = {2007},
issn = {1522-8681},
pages = {117-128},
doi = {http://doi.ieeecomputersociety.org/10.1109/ASYNC.2007.10},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Asynchronous Circuits and Systems, International Symposium on
TI - Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis
SN - 1522-8681
SP117
EP128
A1 - Tiberiu Chelcea,
A1 - Girish Venkataramani,
A1 - Seth C. Goldstein,
PY - 2007
KW - null
VL - 0
JA - Asynchronous Circuits and Systems, International Symposium on
ER -
 
Tiberiu Chelcea, Carnegie Mellon University
Girish Venkataramani, Carnegie Mellon University
Seth C. Goldstein, Carnegie Mellon University
Future deep sub-micron technologies will be characterized by large parametric variations, which could make asynchronous design an attractive solution for use on large scale. However, the investment in asynchronous CAD tools does not approach that in synchronous ones. Even when asynchronous tools leverage existing synchronous toolflows, they introduce large area and speed overheads. This paper proposes several heuristic and optimal algorithms, based on timing interval analysis, for improving existing asynchronous CAD solutions by optimizing area. The optimized circuits are 2.4 times smaller for an optimal algorithm and 1.8 times smaller for a heuristic one than the existing solutions. The optimized circuits are also shown to be resilient to large parametric variations, yielding better average-case latencies than their synchronous counterparts.
Citation:
Tiberiu Chelcea, Girish Venkataramani, Seth C. Goldstein, "Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis," async, pp.117-128, 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07), 2007
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