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A Jitter Attenuating Timing Chain
Berkeley, California March 12-March 14
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASYNC.2007.813th IEEE International Symposium on ...
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Suwen Yang, SUN Microsystems, and NSERC
Mark R. Greenstreet, SUN Microsystems, and NSERC
Jihong Ren, Intel
A long chain of inverters and wire segments will amplify clock jitter and drop timing pulses due to intersymbol interference. We present a jitter attenuating buffer based on surfing techniques. Our buffer circuit consists of a few inverters with variable output strength that implement a simple, low-gain DLL. Chains of these surfing buffers attenuate jitter making them well suited for source-synchronous interfaces. Furthermore, our chains can be used to reliably transmit handshaking signals and support sliding-window protocols to improve the throughput of asynchronous communication.
Citation:
Suwen Yang, Mark R. Greenstreet, Jihong Ren, "A Jitter Attenuating Timing Chain," async, pp.25-38, 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07), 2007
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