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Design of a CMOS Operational Amplifier for Extreme-Voltage Stress Test
Calcutta, India December 18-December 21
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.2005.4914th Asian Test Symposium (ATS'05)
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Shaolei Quan, Michigan State University, US
Qiang Qiang, Synopsys, Inc.
Chin-Long Wey, Natinal Central University, Taiwan
Previous work on extreme-voltage stress test of analog ICs has suffered either from time-costly circuit-level simulation or from the considerable number of bits in the control signal added to circuit for stress operation. This paper presents several fully-stressable circuit structures the appropriate use of which in analog ICs eliminates the need for extra control bits. Based on proposed circuit concepts an operational amplifier is designed in TSMC 0.18?m CMOS technology and is simulated with HSPICE. Simulation results have shown that the designed operational amplifier is fully stressable with minor performance degradation.
Citation:
Shaolei Quan, Qiang Qiang, Chin-Long Wey, "Design of a CMOS Operational Amplifier for Extreme-Voltage Stress Test," ats, pp.70-75, 14th Asian Test Symposium (ATS'05), 2005
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