A New Multi-Processor Architecture for Parallel Lazy Cyclic Reference Counting

Rio de Janeiro, Brazil October 24-October 27

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http://doi.ieeecomputersociety.org/10.1109/CAHPC.2005.6

17th International Symposium on Compu ...

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	Rafael Dueire Lins, "A New Multi-Processor Architecture for Parallel Lazy Cyclic Reference Counting," Computer Architecture and High Performance Computing, Symposium on, pp. 35-43, 17th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'05), 2005.

	BibTex	x
	@article{ 10.1109/CAHPC.2005.6, author = {Rafael Dueire Lins}, title = {A New Multi-Processor Architecture for Parallel Lazy Cyclic Reference Counting}, journal ={Computer Architecture and High Performance Computing, Symposium on}, volume = {0}, year = {2005}, issn = {1550-6533}, pages = {35-43}, doi = {http://doi.ieeecomputersociety.org/10.1109/CAHPC.2005.6}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Computer Architecture and High Performance Computing, Symposium on TI - A New Multi-Processor Architecture for Parallel Lazy Cyclic Reference Counting SN - 1550-6533 SP35 EP43 A1 - Rafael Dueire Lins, PY - 2005 KW - null VL - 0 JA - Computer Architecture and High Performance Computing, Symposium on ER -

Rafael Dueire Lins, Universidade Federal de Pernambuco Recife, PE, Brazil

Reference counting is the memory management technique of most widespread use today. This paper presents a new multi-processor architecture for parallel cyclic reference counting. In this architecture, there is no direct Mutator-Collector communication and synchronization is kept minimal.

Citation:

Rafael Dueire Lins, "A New Multi-Processor Architecture for Parallel Lazy Cyclic Reference Counting," sbac-pad, pp.35-43, 17th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'05), 2005

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