T. Komuro, Dept. of Math. Eng. & Inf. Phys., Tokyo Univ., Japan
I. Ishii, Dept. of Math. Eng. & Inf. Phys., Tokyo Univ., Japan
M. Ishikawa, Dept. of Math. Eng. & Inf. Phys., Tokyo Univ., Japan
A. Yoshida, Dept. of Math. Eng. & Inf. Phys., Tokyo Univ., Japan
This paper describes a new vision chip architecture for high speed target tracking. The system speed and pixel size improved by hardware implementation of a special algorithm which utilizes a property of high speed vision. Using an asynchronous and bit-serial propagation method, global moments of the image are calculated at high speed and with small circuits. Based on the new architecture a 64/spl times/64 pixel prototype chip has been developed.
Index Terms:
target tracking; target tracking; vision chip; chip architecture; high speed target tracking
Citation:
T. Komuro, I. Ishii, M. Ishikawa, A. Yoshida, "High Speed Target Tracking Vision Chip," camp, pp.49, Fifth IEEE International Workshop on Computer Architectures for Machine Perception (CAMP'00), 2000