Implementing Neural Networks in hardware has been a major problem due to the complexity involved in generating non-linear functions. The high hardware costs incurred in real time applications can be substantially reduced by adopting a suitable reuse methodology of the neurons. In addition, neurons with high speed of operation are necessitated to realise hardware efficient real time pattern recognition for images with higher resolution. In this regard, the response time and area of a neuron becomes critical in realising VLSI efficient neural networks. In this paper, the digital architecture of a multiple valued logic neuron has been proposed to realise a neural network implementation for real-time pattern recognition purposes. The proposed neuron uses a multilevel sigmoidal function as the activation function. Flat CORDIC, a new variation of the CORDIC algorithm, has been employed to generate the complex multi-level activation function in a VLSI efficient manner. The proposed neuron operates with a 200 MHz clock and has significant hardware and latency savings when compared to conventional CORDIC based neurons.