A hardware implementation of an Adaptive Noise Canceller (ANC) is presented. It has been synthesized within an FPGA, using a modified version of the Least Mean Square (LMS) error algorithm. The results obtained so far show a significant decrease of the required gate count when compared with a standard LMS implementation, while increasing the ANC bandwidth and signal to noise (S/N) ratio. This novel Adaptive Noise Canceller is then useful for enhancing the S/N ratio of data collected from sensors (or sensor arrays) working in noisy environment, or dealing with potentially weak signals.
Citation:
Antonio Di Stefano, Alessandro Scaglione, Costantino Giaconia, "Efficient FPGA Implementation of an Adaptive Noise Canceller," camp, pp.87-89, Seventh International Workshop on Computer Architecture for Machine Perception (CAMP'05), 2005