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Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache
San Jose, California March 20-March 23
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/CGO.2005.13International Symposium on Code Gener ...
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Rajiv A. Ravindran, University of Michigan, Ann Arbor
Pracheeti D. Nagarkar, University of Michigan, Ann Arbor
Ganesh S. Dasika, University of Michigan, Ann Arbor
Eric D. Marsman, University of Michigan, Ann Arbor
Robert M. Senger, University of Michigan, Ann Arbor
Scott A. Mahlke, University of Michigan, Ann Arbor
Richard B. Brown, University of Utah, Salt Lake City
Modern embedded microprocessors use low power on-chip memories called scratch-pad memories to store frequently executed instructions and data. Unlike traditional caches, scratch-pad memories lack the complex tag checking and comparison logic, thereby proving to be efficient in area and power. In this work, we focus on exploiting scratch-pad memories for storing hot code segments within an application. Static placement techniques focus on placing the most frequently executed portions of programs into the scratch-pad. However, static schemes are inherently limited by not allowing the contents of the scratch-pad memory to change at run time. In a large fraction of applications, the instruction memory footprints exceed the scratch-pad memory size, thereby limiting the usefulness of the scratch-pad. We propose a compiler managed dynamic placement algorithm, wherein multiple hot code sequences, or traces, are overlapped with each other in the scratch-pad memory at different points in time during execution. Special copy instructions are provided to copy the traces into the scratch-pad memory at run-time. Using a power estimate, the compiler initially selects the most frequent traces in an application for relocation into the scratch-pad memory. Through iterative code motion and redundancy elimination, copy instructions are inserted in infrequently executed regions of the code. For a 64-byte code cache, the compiler managed dynamic placement achieves an average of 64% energy improvement over the static solution in a low-power embedded microcontroller.
Citation:
Rajiv A. Ravindran, Pracheeti D. Nagarkar, Ganesh S. Dasika, Eric D. Marsman, Robert M. Senger, Scott A. Mahlke, Richard B. Brown, "Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache," cgo, pp.179-190, International Symposium on Code Generation and Optimization (CGO'05), 2005
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