A 4-Bits CSA Adder Using the Arithmetic A2 Redundant Binary Representation for Mixed Neural Networks with On-Chip Learning

June 26-June 28

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http://doi.ieeecomputersociety.org/10.1109/CISIM.2008.18

2008 7th Computer Information Systems ...

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	Hatem Boukadida, Zied Gafsi, N?jib Hassen, Kamel Besbes, "A 4-Bits CSA Adder Using the Arithmetic A2 Redundant Binary Representation for Mixed Neural Networks with On-Chip Learning," Computer Information Systems and Industrial Management Applications, International Conference on, pp. 97-98, 2008 7th Computer Information Systems and Industrial Management Applications, 2008.

	BibTex	x
	@article{ 10.1109/CISIM.2008.18, author = {Hatem Boukadida and Zied Gafsi and N?jib Hassen and Kamel Besbes}, title = {A 4-Bits CSA Adder Using the Arithmetic A2 Redundant Binary Representation for Mixed Neural Networks with On-Chip Learning}, journal ={Computer Information Systems and Industrial Management Applications, International Conference on}, volume = {0}, year = {2008}, isbn = {978-0-7695-3184-7}, pages = {97-98}, doi = {http://doi.ieeecomputersociety.org/10.1109/CISIM.2008.18}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Computer Information Systems and Industrial Management Applications, International Conference on TI - A 4-Bits CSA Adder Using the Arithmetic A2 Redundant Binary Representation for Mixed Neural Networks with On-Chip Learning SN - 978-0-7695-3184-7 SP97 EP98 A1 - Hatem Boukadida, A1 - Zied Gafsi, A1 - N?jib Hassen, A1 - Kamel Besbes, PY - 2008 KW - neural networks KW - redundant binary representations KW - arithmetic circuits VL - 0 JA - Computer Information Systems and Industrial Management Applications, International Conference on ER -

This paper presents a time-efficient 4-bits carry select adder (CSA) using the arithmetic A2 redundant binary representation. This structure is very suitable for implementation in VLSI of simple mixed-signal neural networks with on-chip learning. This adder is based on a classical weighted binary carry-select adder with two input/output trans-coders. Comparisons with another FPGA-based A2 adder show that the proposed CMOS structure offers a significant increase in speed, while consuming a little more area.

Index Terms:

neural networks, redundant binary representations, arithmetic circuits

Citation:

Hatem Boukadida, Zied Gafsi, N?jib Hassen, Kamel Besbes, "A 4-Bits CSA Adder Using the Arithmetic A2 Redundant Binary Representation for Mixed Neural Networks with On-Chip Learning," cisim, pp.97-98, 2008 7th Computer Information Systems and Industrial Management Applications, 2008

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