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A Formal Approach to Verify Mapping Relation in a Software Product Line
Aizu-Wakamatsu City, Fukushima, Japan October 16-October 19
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/CIT.2007.1117th IEEE International Conference on ...
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Tonny Kurniadi Satyananda, Information and Communications University, Korea
Danhyung Lee, Information and Communications University, Korea
Sungwon Kang, Information and Communications University, Korea
In software product line development, consistency among artifacts is important because commonalities and variabilities increase the complexity of relations among artifacts. For small scale models, the relations among elements can be easily identified and tracked by manually analyzing the descriptions of models. But when the complexity of models is high, a more systematic approach is required for identifying traceability information and verifying consistency between models. In this paper, by utilizing Formal Concept Analysis (FCA) and Prototype Verification System (PVS), we present a formal approach for identifying traceability and verifying consistency between feature model and component and connector view of software architecture.
Citation:
Tonny Kurniadi Satyananda, Danhyung Lee, Sungwon Kang, "A Formal Approach to Verify Mapping Relation in a Software Product Line," cit, pp.934-939, 7th IEEE International Conference on Computer and Information Technology (CIT 2007), 2007
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