The increasing popularity of the Internet and networking has resulted in a significant growth in Internet traffic, coupled with an increase in the number of Internet routers. The increase in routers has resulted in the development of more complex routing algorithms, larger routing tables (requiring more memory), ultimately increasing the time required to search the lookup table. The Cartesian network is an attempt to overcome these problems. Instead of improving the search algorithm, it entirely removes the need for a table lookup. The Cartesian unicast routing algorithm is a novel routing methodology in which a packet?s route is determined by the position of the router relative to that of the destination. This paper describes the hardware design, development, and implementation of the Cartesian routers. A parallel architecture is proposed for the Cartesian routers. Field Programmable Gate Arrays (FPGA) devices are selected as a target platform for hardware implementation.