Interconnect lengths have become a dominant factor in the design of integrated circuits. The parasitics associated with interconnects account for a significant part of the noise, delay and power associated with a signal. The estimation of interconnect lengths prior to placement helps in determining the performance of the circuit early in the design phase. Such estimations can provide circuit optimizations by re-ordering of logic blocks and thus reduce iterations between layout and synthesis. This paper presents a methodology to estimate the individual interconnect lengths in digital ICs, prior to layout. Estimations are from gate level netlist, and properties of a standard cell library. Various layouts have been studied to observe typical placement and routing patterns and these have been incorporated into our estimation methodology. Results obtained from the implementation of the methodology presented were compared with detailed routing wire lengths obtained after actual synthesis of the gate level netlist.