Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs

Munich, Germany March 07-March 11

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http://doi.ieeecomputersociety.org/10.1109/DATE.2005.106

Design, Automation and Test in Europe ...

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	J?rgen Schnerr, Oliver Bringmann, Wolfgang Rosenstiel, "Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs," Design, Automation and Test in Europe Conference and Exhibition, vol. 2, pp. 792-797, Design, Automation and Test in Europe (DATE'05) Volume 2, 2005.

	BibTex	x
	@article{ 10.1109/DATE.2005.106, author = {J?rgen Schnerr and Oliver Bringmann and Wolfgang Rosenstiel}, title = {Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {2}, year = {2005}, issn = {1530-1591}, pages = {792-797}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2005.106}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs SN - 1530-1591 SP792 EP797 A1 - J?rgen Schnerr, A1 - Oliver Bringmann, A1 - Wolfgang Rosenstiel, PY - 2005 KW - null VL - 2 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

J?rgen Schnerr, FZI Forschungszentrum Informatik, Germany

Oliver Bringmann, FZI Forschungszentrum Informatik, Germany

Wolfgang Rosenstiel, FZI Forschungszentrum Informatik, Germany; Universit?t T?bingen, Germany

In this paper, the application of a cycle accurate binary translator for rapid prototyping of SoCs will be presented. This translator generates code to run on a rapid prototyping system consisting of a VLIW processor and FPGAs. The generated code is annotated with information that triggers cycle generation for the hardware in parallel to the execution of the translated program. The VLIW processor executes the translated program whereas the FPGAs contain the hardware for the parallel cycle generation and the bus interface that adapts the bus of the VLIW processor to the SoC bus of the emulated processor core.

Citation:

J?rgen Schnerr, Oliver Bringmann, Wolfgang Rosenstiel, "Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs," date, vol. 2, pp.792-797, Design, Automation and Test in Europe (DATE'05) Volume 2, 2005

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