loading...
A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification
Munich, Germany March 07-March 11
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2005.11Design, Automation and Test in Europe ...
 This Article 
 
Buy PURCHASE ARTICLE: $19
PDF
HTML
Buy IEEE Xplore Subscribers
 
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
ASCII Text
x 
 
Kees Goossens, John Dielissen, Om Prakash Gangwal, Santiago Gonz?lez Pestana, Andrei Radulescu, Edwin Rijpkema, "A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification," Design, Automation and Test in Europe Conference and Exhibition, vol. 2, pp. 1182-1187, Design, Automation and Test in Europe (DATE'05) Volume 2, 2005.
 
 
BibTex
x
 
@article{ 10.1109/DATE.2005.11,
author = {Kees Goossens and John Dielissen and Om Prakash Gangwal and Santiago Gonz?lez Pestana and Andrei Radulescu and Edwin Rijpkema},
title = {A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification},
journal ={Design, Automation and Test in Europe Conference and Exhibition},
volume = {2},
year = {2005},
issn = {1530-1591},
pages = {1182-1187},
doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2005.11},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Design, Automation and Test in Europe Conference and Exhibition
TI - A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification
SN - 1530-1591
SP1182
EP1187
A1 - Kees Goossens,
A1 - John Dielissen,
A1 - Om Prakash Gangwal,
A1 - Santiago Gonz?lez Pestana,
A1 - Andrei Radulescu,
A1 - Edwin Rijpkema,
PY - 2005
KW - null
VL - 2
JA - Design, Automation and Test in Europe Conference and Exhibition
ER -
 
Kees Goossens, Philips Research Laboratories, Eindhoven, The Netherlands
John Dielissen, Philips Research Laboratories, Eindhoven, The Netherlands
Om Prakash Gangwal, Philips Research Laboratories, Eindhoven, The Netherlands
Santiago Gonz?lez Pestana, Philips Research Laboratories, Eindhoven, The Netherlands
Andrei Radulescu, Philips Research Laboratories, Eindhoven, The Netherlands
Edwin Rijpkema, Philips Research Laboratories, Eindhoven, The Netherlands
Systems on chip (SOC) are composed of intellectual property blocks (IP) and interconnect. While mature tooling exists to design the former, tooling for interconnect design is still a research area. In this paper we describe an operational design flow that generates and configures application-specific network on chip (NOC) instances, given application communication requirements. The NOC can be simulated in SystemC and RTL VHDL. An independent performance verification tool verifies analytically that the NOC instance (hardware) and its configuration (software) together meet the application performance requirements. The ?thereal NOC's guaranteed performance is essential to replace time-consuming simulation by fast analytical performance validation. As a result, application-specific NOCs that are guaranteed to meet the application's communication requirements are generated and verified in minutes, reducing the number of design iterations. A realistic MPEG SOC example substantiates our claims.
Citation:
Kees Goossens, John Dielissen, Om Prakash Gangwal, Santiago Gonz?lez Pestana, Andrei Radulescu, Edwin Rijpkema, "A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification," date, vol. 2, pp.1182-1187, Design, Automation and Test in Europe (DATE'05) Volume 2, 2005
Usage of this product signifies your acceptance of the Terms of Use.