Important classes of algorithms which can benefit from the advantages of C-to-VHDL compiling are window operations. These execute a number of instructions on a large amount of array data. Since arrays are usually translated into FPGA block memory structures, it is important to minimize the required number of block memory accesses. Recently, a smart buffer has been introduced, in which a number of past and present array elements can be temporarily stored to be reused over a number of different loop nest iterations. In this paper, the smart buffer approach is analysed for use in the stream-oriented Impulse-C compiler. Experimental automatic generation of VHDL code for this buffer is described. The smart buffer is then linked with the VHDL code generated by the Impulse-C compiler to obtain data efficient designs.