loading...
Architecture of a Low Storage Digital Pixel Sensor Array with an On-Line Block-Based Compression
January 23-January 25
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DELTA.2008.1174th IEEE International Symposium on E ...
 This Article 
 
Buy PURCHASE ARTICLE: $19
PDF
HTML
Buy IEEE Xplore Subscribers
 
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
ASCII Text
x 
 
Milin Zhang, Amine Bermak, "Architecture of a Low Storage Digital Pixel Sensor Array with an On-Line Block-Based Compression," Electronic Design, Test and Applications, IEEE International Workshop on, pp. 167-170, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), 2008.
 
 
BibTex
x
 
@article{ 10.1109/DELTA.2008.117,
author = {Milin Zhang and Amine Bermak},
title = {Architecture of a Low Storage Digital Pixel Sensor Array with an On-Line Block-Based Compression},
journal ={Electronic Design, Test and Applications, IEEE International Workshop on},
volume = {0},
year = {2008},
isbn = {978-0-7695-3110-6},
pages = {167-170},
doi = {http://doi.ieeecomputersociety.org/10.1109/DELTA.2008.117},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Electronic Design, Test and Applications, IEEE International Workshop on
TI - Architecture of a Low Storage Digital Pixel Sensor Array with an On-Line Block-Based Compression
SN - 978-0-7695-3110-6
SP167
EP170
A1 - Milin Zhang,
A1 - Amine Bermak,
PY - 2008
KW - DPS
KW - low storage
KW - block-based compression
KW - error propagation
VL - 0
JA - Electronic Design, Test and Applications, IEEE International Workshop on
ER -
 
In this paper, a block-based architecture of digital pixel sensor (DPS) array integrated with an on-line compression algorithm is proposed. The proposed technique is based on a block divided storage and compression scheme of the original image. Image capture, storage, and reordering are completed simultaneously and performed on-line while storing pixel value into the on-chip memory array. More than 60% of memory saving is achieved using the proposed block-based design. Furthermore, block-based design greatly reduces the accumulation error inherent in DPCM type of processing. Simulation results show that the PSNR result can reach around 30dB with a compression ratio of less than 3 BPP.
Index Terms:
DPS, low storage, block-based compression, error propagation
Citation:
Milin Zhang, Amine Bermak, "Architecture of a Low Storage Digital Pixel Sensor Array with an On-Line Block-Based Compression," delta, pp.167-170, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), 2008
Usage of this product signifies your acceptance of the Terms of Use.