A Design of 14-bits ADC and DAC for CODEC Applications in 0.18 ?m CMOS Process

January 23-January 25

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http://doi.ieeecomputersociety.org/10.1109/DELTA.2008.124

4th IEEE International Symposium on E ...

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	ASCII Text	x
	DongHyun Ko, JiHoon Jung, YoungGun Pu, SangKyung Sung, KangYoon Lee, Chul Nam, "A Design of 14-bits ADC and DAC for CODEC Applications in 0.18 ?m CMOS Process," Electronic Design, Test and Applications, IEEE International Workshop on, pp. 3-6, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), 2008.

	BibTex	x
	@article{ 10.1109/DELTA.2008.124, author = {DongHyun Ko and JiHoon Jung and YoungGun Pu and SangKyung Sung and KangYoon Lee and Chul Nam}, title = {A Design of 14-bits ADC and DAC for CODEC Applications in 0.18 ?m CMOS Process}, journal ={Electronic Design, Test and Applications, IEEE International Workshop on}, volume = {0}, year = {2008}, isbn = {978-0-7695-3110-6}, pages = {3-6}, doi = {http://doi.ieeecomputersociety.org/10.1109/DELTA.2008.124}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Electronic Design, Test and Applications, IEEE International Workshop on TI - A Design of 14-bits ADC and DAC for CODEC Applications in 0.18 ?m CMOS Process SN - 978-0-7695-3110-6 SP3 EP6 A1 - DongHyun Ko, A1 - JiHoon Jung, A1 - YoungGun Pu, A1 - SangKyung Sung, A1 - KangYoon Lee, A1 - Chul Nam, PY - 2008 KW - ADC(Analog-to-Digital Converter) KW - DAC (Digital-to-Analog Converter) KW - Sigma-Delta Modulator VL - 0 JA - Electronic Design, Test and Applications, IEEE International Workshop on ER -

This paper presents a sigma-delta modulation ADC(Analog-to-Digital Converter) and DAC(Digital-to-Analog Converter) for CODEC applications using 0.18um CMOS process. In the ADC parts, two sigma-delta modulators with 84dB SNR are designed for the stereo applications, and their outputs are merged at the digital domain before decimation filter. Digital decimation filter is integrated with the analog sigma-delta modulators for the full ADC operation. In the DAC parts, the digital data is first processed at the interpolator filters, and modulated by the following sigma-delta modulators. To reduce the mismatch effect of the following DAC, the dynamic element matching method is proposed in this paper. It is designed with 0.18 ?m CMOS process. The simulated SNR is about 100dB, and the power consumption is 40 mA.

Index Terms:

ADC(Analog-to-Digital Converter), DAC (Digital-to-Analog Converter), Sigma-Delta Modulator

Citation:

DongHyun Ko, JiHoon Jung, YoungGun Pu, SangKyung Sung, KangYoon Lee, Chul Nam, "A Design of 14-bits ADC and DAC for CODEC Applications in 0.18 ?m CMOS Process," delta, pp.3-6, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), 2008

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