This paper describes a low cost, high quality at-speed testing strategy implemented on a gigahertzmicroprocessor with multi-clock domains. Thepresented DFT method not only utilizes the internal phase-locked loops (PLLs) to provide complex test clock sequences, but also applies a hybrid scan compression structure to reduce test data volume. It is difficult and time-consuming to generate at-speed tests for a design with embedded memories and multi-clock domains. The proposed test pattern generation scheme can gain transition fault coverage of approximately83% for this high-performance microprocessor, andthe test power consumption is well controlled.