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A 14-bit 320 MSPS Segmented Current-Steering D/A Converter for High-Speed Applications
January 23-January 25
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DELTA.2008.434th IEEE International Symposium on E ...
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Liang Shangquan, Gao Minglun, Yin Yongsheng, Deng Honghui, "A 14-bit 320 MSPS Segmented Current-Steering D/A Converter for High-Speed Applications," Electronic Design, Test and Applications, IEEE International Workshop on, pp. 111-114, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), 2008.
 
 
BibTex
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@article{ 10.1109/DELTA.2008.43,
author = {Liang Shangquan and Gao Minglun and Yin Yongsheng and Deng Honghui},
title = {A 14-bit 320 MSPS Segmented Current-Steering D/A Converter for High-Speed Applications},
journal ={Electronic Design, Test and Applications, IEEE International Workshop on},
volume = {0},
year = {2008},
isbn = {978-0-7695-3110-6},
pages = {111-114},
doi = {http://doi.ieeecomputersociety.org/10.1109/DELTA.2008.43},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Electronic Design, Test and Applications, IEEE International Workshop on
TI - A 14-bit 320 MSPS Segmented Current-Steering D/A Converter for High-Speed Applications
SN - 978-0-7695-3110-6
SP111
EP114
A1 - Liang Shangquan,
A1 - Gao Minglun,
A1 - Yin Yongsheng,
A1 - Deng Honghui,
PY - 2008
KW - segmented current-steering
KW - pseudorandom switching sequence
KW - current switch driving circuit
KW - unit current-cell
VL - 0
JA - Electronic Design, Test and Applications, IEEE International Workshop on
ER -
 
A 14-bit, 320 MSPS digital-to-analog converter is designed for high-speed applications. Considering the trade-off among linearity, dynamic performance, chip area, and power dissipation, the proposed DAC employs 5+4+5 segmented structure. The paper focuses on the design of several key circuits, and presents the experiment results (DNL=?2.0 LSB ,INL=?2.7 LSB, SFDR=72.6 dB @ fdata=320 MSPS,fout=4.375 MHz) based on the SMIC 0.35?m Mixed Signal 2P3M CMOS process model. The chip has been fabricated in the SMIC 3.3 V technology with an active area of 2.6?2.6 mm2.
Index Terms:
segmented current-steering, pseudorandom switching sequence, current switch driving circuit, unit current-cell
Citation:
Liang Shangquan, Gao Minglun, Yin Yongsheng, Deng Honghui, "A 14-bit 320 MSPS Segmented Current-Steering D/A Converter for High-Speed Applications," delta, pp.111-114, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), 2008
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