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A Fast Two-Stage Sample-and-Hold Amplifier for Pipelined ADC Application
January 23-January 25
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DELTA.2008.584th IEEE International Symposium on E ...
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Jian Ruan, Chung Len Lee, "A Fast Two-Stage Sample-and-Hold Amplifier for Pipelined ADC Application," Electronic Design, Test and Applications, IEEE International Workshop on, pp. 99-102, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), 2008.
 
 
BibTex
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@article{ 10.1109/DELTA.2008.58,
author = {Jian Ruan and Chung Len Lee},
title = {A Fast Two-Stage Sample-and-Hold Amplifier for Pipelined ADC Application},
journal ={Electronic Design, Test and Applications, IEEE International Workshop on},
volume = {0},
year = {2008},
isbn = {978-0-7695-3110-6},
pages = {99-102},
doi = {http://doi.ieeecomputersociety.org/10.1109/DELTA.2008.58},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Electronic Design, Test and Applications, IEEE International Workshop on
TI - A Fast Two-Stage Sample-and-Hold Amplifier for Pipelined ADC Application
SN - 978-0-7695-3110-6
SP99
EP102
A1 - Jian Ruan,
A1 - Chung Len Lee,
PY - 2008
KW - Sample-and-hold amplifier
KW - Two-stage structure
KW - Pipelined ADC
KW - Bootstrapped switch
KW - Bottom-plate sampling
VL - 0
JA - Electronic Design, Test and Applications, IEEE International Workshop on
ER -
 
This paper presents a differential input, two-stage structure sample-hold-amplifier (SHA) for which each stage can be designed and adjusted separately to have a large input dynamic range and fast operation speed. The clock feed through and charge injection is eliminated. The implemented SHA with a 0.18um 1.8V process shows that it can sample a 2.5 MHz signal at 40 MHz with a 63dB SFDR and a -62 dB THD which is able to realize an ADC of 10 bit resolution.
Index Terms:
Sample-and-hold amplifier, Two-stage structure, Pipelined ADC, Bootstrapped switch, Bottom-plate sampling
Citation:
Jian Ruan, Chung Len Lee, "A Fast Two-Stage Sample-and-Hold Amplifier for Pipelined ADC Application," delta, pp.99-102, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), 2008
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