Employing On-Chip Jitter Test Circuit for Phase Locked Loop Self-Calibration

Arlington, Virginia, USA October 04-October 06

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http://doi.ieeecomputersociety.org/10.1109/DFT.2006.26

21st IEEE International Symposium on ...

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	Tian Xia, Stephen Wyatt, Rupert Ho, "Employing On-Chip Jitter Test Circuit for Phase Locked Loop Self-Calibration," Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on, pp. 12-19, 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'06), 2006.

	BibTex	x
	@article{ 10.1109/DFT.2006.26, author = {Tian Xia and Stephen Wyatt and Rupert Ho}, title = {Employing On-Chip Jitter Test Circuit for Phase Locked Loop Self-Calibration}, journal ={Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on}, volume = {0}, year = {2006}, issn = {1550-5774}, pages = {12-19}, doi = {http://doi.ieeecomputersociety.org/10.1109/DFT.2006.26}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on TI - Employing On-Chip Jitter Test Circuit for Phase Locked Loop Self-Calibration SN - 1550-5774 SP12 EP19 A1 - Tian Xia, A1 - Stephen Wyatt, A1 - Rupert Ho, PY - 2006 KW - null VL - 0 JA - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on ER -

Tian Xia, University of Vermont, USA

Stephen Wyatt, IBM Microelectronics Division, USA

Rupert Ho, IBM Microelectronics Division, USA

In this paper, a new adaptive PLL is implemented. This PLL employs a simple yet effective jitter test circuit to monitor the PLL jitter performance. Additionally, it uses a digital control unit to dynamically adjust the switched loop filter to suppress the jitter. By using this structure, the trade-off between the PLL locking speed and jitter performance can be balanced.

Citation:

Tian Xia, Stephen Wyatt, Rupert Ho, "Employing On-Chip Jitter Test Circuit for Phase Locked Loop Self-Calibration," dft, pp.12-19, 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'06), 2006

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