Dynamic verification architectures provide fault detection by employing a simple checker processor that dynamically checks the computations of a complex processor. For dynamic verification to be viable, the checker processor must keep up with the retirement throughput of the core processor. However, the overall throughput would be limited if the checker processor is neither fast nor wide enough to keep up with the core processor. We investigate the impact of checker bandwidth on performance. As a solution for the checker?s congestion, we propose an Active Verification Management (AVM) approach with a filter checker. The goal of AVM is to reduce overloaded verification in the checker with a congestion avoidance policy and to minimize the performance degradation caused by congestion. Before the verification process starts at the checker processor, a filter checker marks a Correctness Non-criticality Indicator (CNI) bit in advance to indicate how likely these pre-computed results are to be unimportant for reliability. Then AVM decides how to deal with the marked instructions by using a congestion avoidance policy. Both reactive and proactive congestion avoidance policies are proposed to skip the verification process at the checker. Our results show that the proposed AVM has the potential to solve the verification congestion problem when perfect fault coverage is not needed. With no AVM, congestion at the checker badly affects performance, to the tune of 57%, when compared to that of a non-fault-tolerant processor. With good marking by AVM, the performance of a reliable processor approaches 95% of that of a non-fault-tolerant processor. Although instructions can be skipped on a random basis, such an approach reduces the fault coverage. A filter checker with a marking policy correlated with the correctness non-criticality metric, on the other hand, significantly reduces the soft error rate. Finally, we also present results showing the trade-off between performance and reliability.