TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs

Rome, Italy September 26-September 28

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http://doi.ieeecomputersociety.org/10.1109/DFT.2007.25

22nd IEEE International Symposium on ...

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	Cristiana Bolchini, Antonio Miele, Marco D. Santambrogio, "TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs," Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on, pp. 87-95, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007.

	BibTex	x
	@article{ 10.1109/DFT.2007.25, author = {Cristiana Bolchini and Antonio Miele and Marco D. Santambrogio}, title = {TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs}, journal ={Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on}, volume = {0}, year = {2007}, isbn = {0-7695-2885-6}, pages = {87-95}, doi = {http://doi.ieeecomputersociety.org/10.1109/DFT.2007.25}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on TI - TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs SN - 0-7695-2885-6 SP87 EP95 A1 - Cristiana Bolchini, A1 - Antonio Miele, A1 - Marco D. Santambrogio, PY - 2007 KW - null VL - 0 JA - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on ER -

Cristiana Bolchini, Politecnico di Milano

Antonio Miele, Politecnico di Milano

Marco D. Santambrogio, Politecnico di Milano

This paper presents the adoption of the Triple Modular Redundancy coupled with the Partial Dynamic Reconfiguration of Field Programmable Gate Arrays to mitigate the effects of soft errors in such class of device platforms. We propose an exploration of the design space with respect to several parameters (e.g., area and recovery time) in order to select the most convenient way to apply this technique to the device under consideration. The application to a case study is presented and used to exemplify the proposed approach.

Citation:

Cristiana Bolchini, Antonio Miele, Marco D. Santambrogio, "TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs," dft, pp.87-95, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

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