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Evaluation of Register-Level Protection Techniques for the Advanced Encryption Standard by Multi-Level Fault Injections
Rome, Italy September 26-September 28
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DFT.2007.4122nd IEEE International Symposium on ...
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P. Maistri, P. Vanhauwaert, R. Leveugle, "Evaluation of Register-Level Protection Techniques for the Advanced Encryption Standard by Multi-Level Fault Injections," Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on, pp. 499-507, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007.
 
 
BibTex
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@article{ 10.1109/DFT.2007.41,
author = {P. Maistri and P. Vanhauwaert and R. Leveugle},
title = {Evaluation of Register-Level Protection Techniques for the Advanced Encryption Standard by Multi-Level Fault Injections},
journal ={Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on},
volume = {0},
year = {2007},
isbn = {0-7695-2885-6},
pages = {499-507},
doi = {http://doi.ieeecomputersociety.org/10.1109/DFT.2007.41},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
TI - Evaluation of Register-Level Protection Techniques for the Advanced Encryption Standard by Multi-Level Fault Injections
SN - 0-7695-2885-6
SP499
EP507
A1 - P. Maistri,
A1 - P. Vanhauwaert,
A1 - R. Leveugle,
PY - 2007
KW - null
VL - 0
JA - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
ER -
 
P. Maistri, TIMA Laboratory - 46 Avenue F?lix Viallet - 38031 Grenoble Cedex - FRANCE
P. Vanhauwaert, TIMA Laboratory - 46 Avenue F?lix Viallet - 38031 Grenoble Cedex - FRANCE
R. Leveugle, TIMA Laboratory - 46 Avenue F?lix Viallet - 38031 Grenoble Cedex - FRANCE
Some protection techniques had been previously proposed for encryption blocks and applied to an AES encryption IP described at RT Level. One of these techniques had been validated by purely functional fault injections (i.e. algorithmic-level fault injections) against single- and multiple- bit errors. RT-Level fault injections have been performed recently on a few AES IPs and this paper summarizes the main results obtained, highlighting the new results and comparing the outcomes of the two fault injection le
Citation:
P. Maistri, P. Vanhauwaert, R. Leveugle, "Evaluation of Register-Level Protection Techniques for the Advanced Encryption Standard by Multi-Level Fault Injections," dft, pp.499-507, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
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