loading...
The Prediction of Circuit Performance Variations for Deep Submicron CMOS Processes
Boston, MA November 06-November 08
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DFTVS.1996.5720151996 Workshop on Defect and Fault-Tol ...
 This Article 
 
Buy PURCHASE ARTICLE: $19
PDF
HTML
Buy IEEE Xplore Subscribers
 
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
ASCII Text
x 
 
Thomas Gneiting, Ian P. Jalowiecki, "The Prediction of Circuit Performance Variations for Deep Submicron CMOS Processes," Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on, pp. 140, 1996 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT'96), 1996.
 
 
BibTex
x
 
@article{ 10.1109/DFTVS.1996.572015,
author = {Thomas Gneiting and Ian P. Jalowiecki},
title = {The Prediction of Circuit Performance Variations for Deep Submicron CMOS Processes},
journal ={Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on},
volume = {0},
year = {1996},
issn = {1063-6722},
pages = {140},
doi = {http://doi.ieeecomputersociety.org/10.1109/DFTVS.1996.572015},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
TI - The Prediction of Circuit Performance Variations for Deep Submicron CMOS Processes
SN - 1063-6722
SP
EP
A1 - Thomas Gneiting,
A1 - Ian P. Jalowiecki,
PY - 1996
KW - Deep submicron process
KW - CMOS
KW - Statistical Modeling
VL - 0
JA - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
ER -
 
Thomas Gneiting, Fachhochschule fuer Technik Esslingen
Ian P. Jalowiecki, Brunel University of West London
In this paper, a method is described which can be used to predict the variation of circuit performance, e.g. the maximum clock rate, due to fluctuations of the semiconductor manufacturing process. A huge amount of measurements on CMOS test devices of two process generations (0.8 and 0.5 micron) has been performed to develop a description of the statistical variations. Based on this data and the use of a physical simulation model for the MOS devices, a prediction of the circuit performance of two future CMOS process generations (0.35 and 0.25 micron) has been undertaken. At least, the results of this study will be applied to a special type of circuits, to predict the feasability of synchronous clock and data distribution on future ULSI devices.
Index Terms:
Deep submicron process, CMOS, Statistical Modeling
Citation:
Thomas Gneiting, Ian P. Jalowiecki, "The Prediction of Circuit Performance Variations for Deep Submicron CMOS Processes," dft, pp.140, 1996 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT'96), 1996
Usage of this product signifies your acceptance of the Terms of Use.