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Multiple Transient Faults in Logic: An Issue for Next Generation ICs
Monterey, California October 03-October 05
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DFTVS.2005.4720th IEEE International Symposium on ...
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Daniele Rossi, DEIS, University of Bologna
Martin Oma?, DEIS, University of Bologna
Fabio Toma, DEIS, University of Bologna
Cecilia Metra, DEIS, University of Bologna

In this paper, we first evaluate whether or not a multiple Transient Fault (multiple TF) generated by the hit of a single cosmic ray neutron can give rise to a bidirectional error at the circuit output (that is an error in which all erroneous bits are 1s rather than 0s, or vice versa, within the same word, but not both). By means of electrical level simulations we will show that this can be the case. Then, we present a software tool that we have developed in order to evaluate the likelihood of occurrence of such bidirectional errors for Very Deep Submicron (VDSM) ICs. The application of this tool to benchmark circuits has proven that such a probability can not be neglected for several benchmark circuits. Finally, we evaluate the behavior of conventional self-checking circuits (generally designed accounting only for single TFs) with respect to such events. We show that the modifications generally introduced to their functional blocks in order to avoid output bidirectional errors due to single TFs (as required when an AUED code is implemented) can significantly reduce (up to the 40%) also the probability to have bidirectional errors because of multiple TFs.

Citation:
Daniele Rossi, Martin Oma?, Fabio Toma, Cecilia Metra, "Multiple Transient Faults in Logic: An Issue for Next Generation ICs," dft, pp.352-360, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), 2005
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