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A Fast Algorithm for Critical Path Tracing in VLSI Digital Circuits
Monterey, California October 03-October 05
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DFTVS.2005.620th IEEE International Symposium on ...
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Lei Wu, D. M. H. Walker, "A Fast Algorithm for Critical Path Tracing in VLSI Digital Circuits," Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on, pp. 178-186, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), 2005.
 
 
BibTex
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@article{ 10.1109/DFTVS.2005.6,
author = {Lei Wu and D. M. H. Walker},
title = {A Fast Algorithm for Critical Path Tracing in VLSI Digital Circuits},
journal ={Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on},
volume = {0},
year = {2005},
isbn = {0-7695-2464-8},
pages = {178-186},
doi = {http://doi.ieeecomputersociety.org/10.1109/DFTVS.2005.6},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
TI - A Fast Algorithm for Critical Path Tracing in VLSI Digital Circuits
SN - 0-7695-2464-8
SP178
EP186
A1 - Lei Wu,
A1 - D. M. H. Walker,
PY - 2005
KW - null
VL - 0
JA - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
ER -
 
Lei Wu, Texas A&M University
D. M. H. Walker, Texas A&M University

An exact, linear-time critical path tracing algorithm is presented. The performance of critical path tracing is determined primarily by the efficiency of stem analysis. The proposed strategy can determine stem criticality in one pass based on six rules. Experiments on ISCAS85 and ISCAS89 benchmark circuits show that the computation time is nearly linear in the number of nets.

Citation:
Lei Wu, D. M. H. Walker, "A Fast Algorithm for Critical Path Tracing in VLSI Digital Circuits," dft, pp.178-186, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), 2005
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