Abstract: Wave-Steering is a new circuit design methodology to realize high throughput circuits by embedding layout friendly structures in silicon. Latches guarantee correct signal arrival times at the inputs of synthesized modules and maintain the high throughput of operation. This paper presents a global routing technique for networks of wave-steered blocks. Latches can be distributed along interconnects. Their number depends on net topologies and signal ordering at the inputs of wave steered blocks. Here, we route nets using Steiner tree heuristics and determine signal ordering and latch positions on interconnect. The problem of total latch number minimization is solved using SAT formulation. Experimental results on benchmark circuits show the efficiency of our technique. We achieve on average a 40% latch reduction at minimum latency over un-optimized circuits operating at 250 MHz in 0.25?m CMOS technology.