loading...
A processor for testing mixed-signal cores in System-on-Chip
Porto, Portugal August 30-September 03
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DSD.2005.118th Euromicro Conference on Digital S ...
 This Article 
 
PDF
HTML
 
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Francisco Duarte, Universidade do Porto, INESC Porto
J. Machado da Silva, Universidade do Porto, INESC Porto
Jose C. Alves, Universidade do Porto, INESC Porto
G. A. Pinho, Universidade do Porto, INESC Porto
Jose S. Matos, Universidade do Porto, INESC Porto

This paper describes the design of a processor specific for testing cores embedded in system-on-chip. This processor, which can be implemented within a system?s reconfigurable area, shall be responsible for scheduling and control test operations and perform preliminary data processing, as well as to provide the interface with an external tester. Building these test operations on-chip allows for simplifying external tester interface and to reduce testing time. The testing procedure and the infrastructure required to test an A/D converter is described as an example.

Citation:
Francisco Duarte, J. Machado da Silva, Jose C. Alves, G. A. Pinho, Jose S. Matos, "A processor for testing mixed-signal cores in System-on-Chip," dsd, pp.184-191, 8th Euromicro Conference on Digital System Design (DSD'05), 2005
Usage of this product signifies your acceptance of the Terms of Use.