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Novel Modulo 2^n + 1 Multipliers
Cavtat near Dubrovnik, Croatia August 30-September 01
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DSD.2006.719th EUROMICRO Conference on Digital S ...
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H. T. Vergos, C. Efstathiou, "Novel Modulo 2^n + 1 Multipliers," Digital Systems Design, Euromicro Symposium on, pp. 168-175, 9th EUROMICRO Conference on Digital System Design (DSD'06), 2006.
 
 
BibTex
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@article{ 10.1109/DSD.2006.71,
author = {H. T. Vergos and C. Efstathiou},
title = {Novel Modulo 2^n + 1 Multipliers},
journal ={Digital Systems Design, Euromicro Symposium on},
volume = {0},
year = {2006},
isbn = {0-7695-2609-8},
pages = {168-175},
doi = {http://doi.ieeecomputersociety.org/10.1109/DSD.2006.71},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Digital Systems Design, Euromicro Symposium on
TI - Novel Modulo 2^n + 1 Multipliers
SN - 0-7695-2609-8
SP168
EP175
A1 - H. T. Vergos,
A1 - C. Efstathiou,
PY - 2006
KW - null
VL - 0
JA - Digital Systems Design, Euromicro Symposium on
ER -
 
H. T. Vergos, University of Patras, Greece
C. Efstathiou, TEI of Athens, Greece
A new modulo 2^n+1 multiplier architecture is proposed for operands in the normal representation. The novel architecture is derived by showing that all required correction factors can be merged into a single constant one and by treating this, partly as a partial product and partly by the final parallel adder. The proposed architecture utilizes a total of (n+1) partial products, each n bits wide and is built using an inverted end-around-carry, carry-save adder tree and a final parallel adder.
Citation:
H. T. Vergos, C. Efstathiou, "Novel Modulo 2^n + 1 Multipliers," dsd, pp.168-175, 9th EUROMICRO Conference on Digital System Design (DSD'06), 2006
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