With the ever increasing amounts of information stored on the web or archived within computing systems, high performance data processing architectures are required to process this data in real time. The aim of the work presented in this paper is the development of a hardware text mining IP-Core for use in FPGA based systems. In this paper we will describe the development of our text processing hardware pipeline, with the addition of a complex word stemming and loadable stop list stages. The performance of this system is then compared to our initial prototype and an equivalent software implementation using the Lucene software library.