Scan-Based SoC Test Using Space / Time Pattern Compaction Schemes

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http://doi.ieeecomputersociety.org/10.1109/DSD.2006.83

9th EUROMICRO Conference on Digital S ...

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	C. Galke, U. G?tzschmann, H. T. Vierhaus, "Scan-Based SoC Test Using Space / Time Pattern Compaction Schemes," Digital Systems Design, Euromicro Symposium on, pp. 433-438, 9th EUROMICRO Conference on Digital System Design (DSD'06), 2006.

	BibTex	x
	@article{ 10.1109/DSD.2006.83, author = {C. Galke and U. G?tzschmann and H. T. Vierhaus}, title = {Scan-Based SoC Test Using Space / Time Pattern Compaction Schemes}, journal ={Digital Systems Design, Euromicro Symposium on}, volume = {0}, year = {2006}, isbn = {0-7695-2609-8}, pages = {433-438}, doi = {http://doi.ieeecomputersociety.org/10.1109/DSD.2006.83}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Digital Systems Design, Euromicro Symposium on TI - Scan-Based SoC Test Using Space / Time Pattern Compaction Schemes SN - 0-7695-2609-8 SP433 EP438 A1 - C. Galke, A1 - U. G?tzschmann, A1 - H. T. Vierhaus, PY - 2006 KW - null VL - 0 JA - Digital Systems Design, Euromicro Symposium on ER -

C. Galke, Brandenburg University of Technology Cottbus

U. G?tzschmann, Brandenburg University of Technology Cottbus

H. T. Vierhaus, Brandenburg University of Technology Cottbus

The ever-increasing complexity of Systems on a Chip (SoCs) has driven scan-based logic test technologies to their limits. Built-in self-test is one possible solution to overcome the problem. However, externally controlled test procedures that allow the re-use of existing testers and adaption to changing patterns seem to gain a higher level of industrial acceptance. Then a high degree of test pattern compaction withoutsacrificing test coverage is essential. This paper describes a versatile pattern compaction scheme that is independent from special ATPG tools, can be optimized for either hard-to-test versus large circuits and can even accommodate bit settings in LFSR outputs.

Citation:

C. Galke, U. G?tzschmann, H. T. Vierhaus, "Scan-Based SoC Test Using Space / Time Pattern Compaction Schemes," dsd, pp.433-438, 9th EUROMICRO Conference on Digital System Design (DSD'06), 2006

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