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Efficient Utilization of Scratch-Pad Memory in Embedded Processor Applications
March 17-March 20
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/EDTC.1997.5823231997 European Design and Test Confere ...
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Preeti Ranjan Panda, Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
Nikil D. Dutt, Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
Alexandru Nicolau, Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
Efficient utilization of on-chip memory space is extremely important in modern embedded system applications based on microprocessor cores. In addition to a data cache that interfaces with slower off-chip memory, a fast on-chip SRAM, called Scratch-Pad memory, is often used in several applications. We present a technique for efficiently exploiting on-chip Scratch-Pad memory by partitioning the application's scalar and array variables into off-chip DRAM and on-chip Scratch-Pad SRAM, with the goal of minimizing the total execution time of embedded applications. Our experiments on code kernels from typical applications show that our technique results in significant performance improvements.
Index Terms:
microprocessor chips, embedded processor, microprocessor core, on-chip scratch-pad memory, SRAM, execution time, code kernel, partitioning
Citation:
Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau, "Efficient Utilization of Scratch-Pad Memory in Embedded Processor Applications," edtc, pp.7, 1997 European Design and Test Conference (ED&TC '97), 1997
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