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Multiplier Block Synthesis Using Evolutionary Graph Generation
Seattle, Washington, USA June 24-June 26
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/EH.2004.13108122004 NASA/DoD Conference on Evolvable ...
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Naofumi Homma, Tohoku University, Japan
Takafumi Aoki, Tohoku University, Japan
Tatsuo Higuchi, Tohoku Institute of Technology, Japan
This paper presents a graph-based evolutionary optimization technique, called Evolutionary Graph Generation (EGG), and its application to hierarchical synthesis of arithmetic circuits. In stead of creating bit-level circuits directly, the EGG system generates arithmetic data-flow graphs that can be transformed into actual bit-level circuit configurations. The potential capability of EGG has been investigated through an experiment of synthesizing multiplier blocks which are used in many DSP applications.
Citation:
Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi, "Multiplier Block Synthesis Using Evolutionary Graph Generation," eh, pp.79, 2004 NASA/DoD Conference on Evolvable Hardware (EH'04), 2004
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